In today’s era of rapid electronics innovation, the Printed Circuit Board (PCB) serves as the foundational “skeleton” of every electronic device. Its manufacturing process directly impacts product performance, reliability, and cost. With trends like high-speed signaling, high-density integration, and green manufacturing accelerating, modern PCB fabrication has evolved far beyond simple “copper etching.” This article provides a systematic overview of current PCB manufacturing workflows, key specifications, and design best practices—based on real-world capabilities from leading 2025 PCB fabricators such as JLCPCB—to help engineers avoid manufacturability pitfalls early in the design phase and improve production yield.
For hardware engineers, mastering PCB fabrication isn’t just about knowing how it’s done—it’s about understanding why certain design choices matter. The benefits include:
Cost Control: Standard processes can be several times cheaper than pushing fabrication limits.
Higher Yield: Avoiding issues like short circuits, open traces, or poor via plating due to unmanufacturable designs.
Design Guidance: Setting appropriate trace widths, clearances, via sizes, and solder mask openings ensures Design for Manufacturability (DFM).
Key Terminology:
Standard Parameters: 1 oz copper (35 µm), minimum drill size ≥0.3 mm, trace/space ≥6 mil (0.15 mm)—recommended for most designs.
Capability Limits: Represent the absolute extremes a manufacturer can achieve (e.g., 0.15 mm drills), but often come with lower yields and higher costs—avoid unless absolutely necessary.
Modern PCB fabrication involves over 14 precision steps. Here are the critical stages:
MI (Manufacturing Instructions) Generation
CAM engineers convert Gerber files into detailed production instructions—the bridge between design and manufacturing.
Panel Cutting & Registration
Large copper-clad laminates are cut to panel size and drilled with registration holes.
Inner Layer Imaging
Dry film lamination → exposure → development → etching forms inner-layer circuitry.
Inner Layer AOI Inspection
Automated Optical Inspection checks for opens, shorts, or defects on inner layers.
Brown Oxide Treatment
Chemical roughening of copper surfaces enhances adhesion to prepreg during lamination.
Lamination
Core layers, prepreg, and copper foil are bonded under heat and pressure into a single multilayer stack.
Drilling
Creates through-holes and component holes. Standard minimum hole size is 0.3 mm; advanced shops can reach 0.15 mm, though micro-drilling is slow and prone to tool breakage.
Through-Hole Plating (PTH)
Electroless copper deposition metallizes hole walls for interlayer connectivity.
Electroplating (Copper Build-Up)
Electrolytic plating thickens both hole walls and surface traces to ensure current-carrying capacity and reliability.
Outer Layer Imaging + Pattern Plating
Another dry-film cycle exposes desired traces, followed by copper and tin plating for protection.
Etching
Unprotected copper is removed, leaving only the final outer-layer traces.
Solder Mask Application
Liquid photoimageable solder mask (typically green) is applied, with openings only at pads to prevent solder bridging.
Silkscreen Printing
Component labels, polarity marks, etc., are printed. Recommended character height: ≥1.0 mm.
Surface Finish
Common options include:
Lead-Free HASL (Hot Air Solder Leveling): Cost-effective and widely used;
ENIG (Electroless Nickel Immersion Gold): Flat surface ideal for BGAs and fine-pitch components;
OSP (Organic Solderability Preservative): Low-cost but limited shelf life—best for fast-turn projects.
Electrical Testing
Flying probe or fixture-based testing verifies no opens or shorts exist.
Routing / Profiling
Panels are depanelized using V-grooves or CNC milling.
Final Quality Control (FQC)
Visual inspection for appearance, dimensions, markings, and compliance.
| Parameter | Recommended Value | Notes |
|---|---|---|
| Finished Copper Thickness | Outer: 1 oz; Inner: 0.5–1 oz | Standard choice |
| Via Hole Size | Drill: 0.3 mm; Pad: 0.5 mm | Best balance of cost & reliability |
| Min Trace/Space | 0.15 mm (6 mil) | Safe for 1 oz copper |
| Through-Hole Annular Ring | ≥0.25 mm (10 mil) | Single-side |
| Via Annular Ring | ≥0.075 mm (3 mil) | Single-side |
| Silkscreen-to-Pad Clearance | ≥0.15 mm (6 mil) | Prevents ink on pads |
| V-Cut to Traces | ≥0.4 mm (16 mil) | Avoids mechanical damage |
Critical Tip: Avoid extremely narrow necks or tight spacing between traces of the same net. Residual dry film can cause “hidden shorts” that electrical tests won’t catch (since they’re not true electrical faults).
For USB, PCIe, DDR, and other high-speed interfaces:
Impedance Control: Use the fabricator’s stackup data to calculate trace widths (e.g., 50 Ω single-ended, 100 Ω differential).
Solid Reference Planes: Keep ground/power planes continuous—avoid splits under high-speed traces.
Differential Pair Length Matching: Tolerance ≤±5 mil recommended.
3W Rule: Maintain ≥3× trace width spacing between high-speed lines to reduce crosstalk.
Always provide the following deliverables:
Gerber RS-274X files (all signal, solder mask, silkscreen, and board outline layers)
NC Drill file
Pick-and-place coordinate file
BOM (for SMT assembly)
Never submit native PCB source files (e.g.,
.PcbDoc)—differences in software versions, fonts, or settings can lead to costly manufacturing errors.
In 2025’s electronics ecosystem, PCB design and fabrication are deeply intertwined. Great hardware engineers don’t just “draw boards”—they design boards that are easy to manufacture, test, and deploy reliably. By adhering to standard process capabilities, respecting DFM guidelines, and selecting appropriate surface finishes, you’ll significantly boost first-pass success rates while optimizing cost and performance.
